In deep sub-micron semiconductor technology, it is a trend to shrink device dimensions, include more functions in a device and decrease power consumption. As more functions are integrated into a chip, a chip often has more power pins to supply sufficient current for circuit operations. These power pins may support different voltage levels of a high-state voltage source VCC or VDD of a chip in various applications. For example, in typical 0.35 μm CMOS technology, the VCC for a chip with a gate-oxide thickness of 70 angstroms has been scaled down to 3.3V. However, the VCC for a chip with a gate-oxide thickness of 140 angstroms may be as high as 5V. The environment in which chips have different power supplies with different voltage levels has been called a mixed voltage interface.
In designing an electrostatic discharge (ESD) protection circuit for a mixed voltage interface, two issues are often taken into consideration: gate oxide reliability and direct current (DC) leakage. However, conventional ESD protection designs for a mixed voltage interface, for example, a 3.3V/1.8V interface, may have some disadvantages, as will be explained below.
FIG. 1 shows a conventional ESD protection circuit using a gate-grounded NMOS and a gate-shorted-to-VDD PMOS to clamp an incoming signal at one diode voltage drop above 1.8V, and conduct an excessive DC leakage current from an input pad to the 1.8V VDD line when a 3.3V signal is applied to the input pad. Such a circuit may have a gate oxide reliability problem because the thin-gate oxide of the gate-grounded NMOS has to sustain the overstress as the drain voltage is 3.3V. To solve the problem, a thick-gate NMOS may be used but will increase the manufacturing cost.
FIG. 2 is a reproduction of FIG. 2 of U.S. Pat. No. 5,780,897 (the '897 patent) to Krakauer, entitled “ESD Protection Clamp for Mixed Voltage I/O Stages Using NMOS Transistors.” The '897 patent describes an electrostatic discharge protection device including two thin-gate NMOS transistors stacked in a cascode configuration. The top transistor of the stacked NMOS includes a drain terminal coupled to an input/output (I/O) pad, a gate (top gate) coupled to a voltage source VDD, and a source coupled to the drain of the bottom transistor of the stacked. That is, the source of the top transistor and the drain of the bottom transistor share one and the same N+ diffusion region. During an ESD event, a parasitic lateral NPN transistor in the ESD protection device is triggered to conduct an ESD current.
FIG. 3 is a reproduction of FIG. 2 of U.S. Pat. No. 5,956,219 (the '219 patent) to Maloney, entitled “High Voltage Power Supply Clamp Circuitry for Electrostatic Discharge (ESD) Protection.” The '219 patent describes an ESD clamp circuit including two thin-gate PMOS transistors without using the thick-gate transistor. In a CMOS process, the thick-gate transistor needs an extra mask in the manufacturing process, which increases the fabrication cost. During normal circuit operating conditions, at least one of the two PMOS transistors is switched off to stop any leakage current. During an ESD event, the two PMOS transistors are switched on to conduct an ESD current. For deep submicron applications, as shown in FIGS. 3 and 4 of the '219 patent, three or more transistors are employed in the ESD clamp circuit to sustain a high power supply voltage.
FIG. 4 is a diagram showing the relationship between a second breakdown current (It2) and a substrate current (Isub) in a substrate-triggered ESD protection device for different channel widths (W). Referring to FIG. 4, It2 increases as Isub increases. Based on this property, substrate-triggered devices have been developed for ESD protection. To apply the substrate-triggered technique to the thin-gate ESD protection devices, however, the chip layout area would have to be increased to accommodate an additional substrate trigger site. It is desired to use the substrate-triggered technique in a thin-gate ESD protection device without increasing the layout area.